As the scale of semiconductor device integration increases, the width of metal interconnections used in the semiconductor device decreases, resulting in an increase of resistance and signal transmission delay in the metal interconnections. To solve the problem of signal transmission delay, a multi-layered interconnection structure may be substituted for single-layered interconnection structures.
However, as distances between metal interconnection layers decrease in the multi-layered interconnection structure, parasitic capacitance and parasitic resistance (impedence) between adjacent metal interconnections in the same layer increase, and therefore, the operational speed of the semiconductor device is reduced. With very fine interconnections in the device, signal transmission delays caused by parasitic capacitance in the interconnections significantly affects the operational characteristics (for example, speed, power consumption, and reliability, among others) of the semiconductor device. In order to reduce the parasitic capacitance between the interconnections, the widths of the interconnections may be reduced and the thickness of interlayer insulating layers may be enlarged. Accordingly, to form interconnections of metal having low resistivity and interlayer insulating films of material having a low dielectric constant, a material such as copper (Cu) may be used as the interconnection material. However, since the vapor pressure of the reactant generated while etching copper is low, dry etching copper is difficult.
Accordingly, a damascene or dual damascene process may be used in forming copper interconnections by forming via holes and/or trenches in an interlayer insulating layer, filling the via holes and/or the trenches with copper and then planarizing the copper with the insulating layer.
Particularly, the dual damascene process includes the steps of forming an etch stop layer over a semiconductor substrate, forming a first silane layer, an insulating layer and a second silane layer thereon, and etching selectively the layers to form via holes therein. Then, the via holes are filled with a photoresist film, and a trench pattern is formed over the second silane layer. Subsequently, using the trench pattern as a mask, an RIE (reactive ion etching) is performed on the second silane layer and the insulating layer to form trenches therein. A barrier metal film is formed over inside walls of the via holes and the trenches, which are then filled with a metal thin film. The metal thin film is then patterned to form metal interconnections to connect to electrodes and pads of the device.
In some instances, individual metal interconnections need to have a resistance different from the others depending on their function. The widths of the metal interconnections may be adjusted individually. When forming metal interconnections having a relatively lower resistance in a single layer, the widths of the interconnections may be adjusted to be wider.
FIGS. 1 and 2 illustrate plan and cross-sectional views of metal interconnections that are fabricated using a dual damascene process.
As shown in FIGS. 1 and 2, metal interconnections 10 and 20 are formed to have different widths, and therefore different resistances. For example, metal interconnection 10 has a width W and a relatively higher resistance while metal interconnection 20 has a width W′ (greater than width W) and a relatively a lower resistance. The metal interconnections are spaced by a minimum distance S.
In general, a minimum design rule is used in forming metal interconnections in semiconductor devices. However, metal interconnections having a lower resistance often need to be formed. These metal interconnections should have a relatively greater width. This also means that the size of the semiconductor device is increased as much as the size for the metal interconnections. For example, when metal interconnections having a lower resistance need to be formed, but without increasing trench depths (see FIG. 2), the widths of those metal interconnections may be enlarged.
However, the chip size of semiconductor devices needs to be minimized to achieve large scale integration, a high yield per wafer, and other advantages. However, it is difficult to increase the integration level, and minimize chip size using a dual damascene process in which the widths of interconnections need to be enlarged.